`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:38:19 04/06/2013 
// Design Name: 
// Module Name:    fpga_top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module fpga_top(
/* INPUTS  */ input [7:0] sw, 
				  input btnLOAD, btnRST, btnGO, clk,
/* OUTPUTS */ output [6:0] seg, output [3:0] an, output [1:0] led
    );

	//Calculated from lab 1
	parameter BUTTONHYS_ON = 60000; 
	parameter BUTTONHYS_OFF = 35000;
	parameter SWITCHHYS_ON = 100000;
	parameter SWITCHHYS_OFF = 240000;
	parameter ECDURATION = 100000000;

	wire i_ec_go;
	wire iEmpty;
	wire iFull;
	
	wire i_fifo_push;
	wire i_fifo_pop;

	wire clk_50MHz;
	
	wire sev_seg_read;
	wire [1:0] sev_seg_addr;
	wire [3:0] sev_seg_data;
	
	wire [7:0] processor_data;
	
	wire [7:0] w_data;
	
	assign led[0] = iFull;
	assign led[1] = iEmpty;
	assign iResetb = !btnRST;

//Go handler
button_pulse_generator # (
	.SIGHYS_OFF(BUTTONHYS_OFF),
	.SIGHYS_ON(BUTTONHYS_ON)
	) bpg_go (
	.i_button(btnGO), 
	.i_clk(clk), 
	.i_resetb(iResetb),
	.o_positive_edge(i_ec_go)
    );

//Load handler
button_pulse_generator # (
	.SIGHYS_OFF(BUTTONHYS_OFF),
	.SIGHYS_ON(BUTTONHYS_ON)
	) bpg_load (
	.i_button(btnLOAD), 
	.i_clk(clk), 
	.i_resetb(iResetb),
	.o_positive_edge(i_fifo_push)
    );

//Switch Latchers
genvar i;
generate 

	for (i = 0; i < 8; i = i + 1) begin : SWITHLATCHER
		switch_latcher  # (
		.SIGHYS_OFF(SWITCHHYS_OFF),
		.SIGHYS_ON(SWITCHHYS_ON)
		) sl (
			 .i_switch(sw[i]), 
			 .i_clk(clk), 
			 .i_resetb(iResetb),
			 .o_latched_data(w_data[i])
			 );
	end
	
endgenerate

//Execution Control
Execution_Control # 
	(
	.duration(ECDURATION)
	)		ec(
    .go(i_ec_go),
    .Sys_clk_100mhz(clk),
    .tx_sucessful(),
    .stop(iEmpty),
	 .rst(iResetb),
    .pop_data(i_fifo_pop)
    );

//Execution_Control #
//	(
//	 .DURATION(ECDURATION), .REGSIZE(26))ec(
//    .go(i_ec_go),
//    .ram_clk(clk),
//    .cpu_clk(clk_50MHz),
//    .stop(iEmpty),
//	 .rst(iResetb),
//    .pop_data(i_fifo_pop)
//    );

asynchronous_FIFO # (
	.DSIZE(8), 
	.ASIZE(4)) fifo (
	.rdata(processor_data), 
	.wfull(iFull), 
	.rempty(iEmpty), 
	.wdata(w_data),
	.winc(i_fifo_push), 
	.wclk(clk), 
	.wrst_n(iResetb), 
	.rinc(i_fifo_pop), 
	.rclk(clk_50MHz), 
	.rrst_n(iResetb)
);
	
//Clock Divider
clock_divider # 
	  (
			.width (0),
			.division (1)
	  )
		  clk_div (
		 .Sys_clk_100mhz(clk),
		 .rst(iResetb),
		 .clk_50mhz (clk_50MHz)
    );

Processor #(.N(4)) proc (
	  .clk(clk_50MHz),
    .pop_data(i_fifo_pop),
    .data_in(processor_data),
	 .rst(iResetb),
    .read(sev_seg_read),
    .read_addr_in(sev_seg_addr),
    .data_out(sev_seg_data)
    );

//7 Segment Display
sev_seg_disp sevseg (
	.clk_50mhz(clk_50MHz),
	.rst(iResetb),
	.read(sev_seg_read),
	.addr(sev_seg_addr),
	.read_data(sev_seg_data),
	.dis_control(an),   
	.led_dis(seg)
);

endmodule
